This application claims priority from Korean Application No. 1999-53754, filed Nov. 30, 1999, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to data buffer circuits, integrated circuit devices and methods of operation thereof.
Conventional integrated circuit memory devices typically provide a read path that includes a sense amplifier, a data multiplexer, data buffer, and data output driver. In response to a data output control signal which acts like an intermittently enabled clock signal, a data buffer typically outputs data received from a sense amplifier via a data multiplexer. In some conventional integrated circuit memory devices, such a data output control signal is generated under control of a clock buffer control signal that enables and disables generation of the clock-like data output control signal. However, when the speed at which such an integrated circuit memory device is increased, timing of such a clock buffer control signal can be corrupted such that the data output control signal is improperly timed with respect to the operation of other devices in the read path.
According to embodiments of the present invention, a data buffer control circuit provides a buffer clock signal to a data buffer of an integrated circuit memory device having a read cycle that is initiated by assertion of a read cycle control signal. The data buffer control circuit comprises a clock buffer circuit that receives an input clock signal and a clock buffer control signal, the clock buffer circuit operative to generate the buffer clock signal from the input clock signal when the clock buffer control signal is in a first state and to prevent generation of the buffer clock signal from the input clock signal when the clock buffer control signal is in a second state. The data buffer control circuit further comprises a clock buffer control circuit that is responsive to the read cycle control signal and to the clock signal and that transitions the clock buffer control signal to the first state responsive to a first transition of the input clock signal following assertion of the read cycle control signal and that transitions the clock buffer control signal to the second state responsive to the end of the predetermined interval. A first half cycle of the input clock signal may commence with the first transition of the input clock signal, and the clock buffer control circuit may be operative to transition the clock buffer control signal to the first state following the first transition of the input clock signal and before the end of the first half cycle of the input clock signal.
According to some embodiments of the present invention, the clock buffer control circuit comprises a read cycle start detection circuit that receives the read cycle control signal and that generates a transition in a read cycle start detection signal responsive to the first transition of the input clock signal following the transition of the read cycle control signal. The clock buffer control circuit further comprises a latch circuit that receives the read cycle start detection signal and generates the first state in the clock buffer control signal responsive to the transition of the read cycle start detection signal.